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SX-A Automotive Family FPGAs
Specifications
* * * * 12,000 to 108,000 Available System Gates Up to 360 User-Programmable I/O Pins Up to 2,012 Dedicated Flip-Flops 0.22 CMOS Process Technology * * * * * Nonvolatile
ue
Configurable I/O Support for 3.3V PCI, 3.3V LVTTL, 2.5V LVCMOS2 Configurable Weak-Resistor Pull-up or Pull-down for Outputs at Power-up Individual Output Slew Rate Control Up to 100% Resource Utilization and 100% Pin Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic Capability with Silicon Explorer II and Verification
Features
* * * * * 250 MHz Internal Performance Hot-Swap Compliant I/Os Power-up/down Friendly (No Sequencing Required for Supply Voltages) 66 MHz PCI Compliant Single-Chip Solution
* * * *
Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Actel's Secure Programming Technology with FuseLockTM Prevents Reverse Engineering and Design Theft
SX-A Automotive-Grade Product Profile
Device Capacity Typical Gates System Gates Logic Modules Combinatorial Cells Register Cells Dedicated Flip-Flops Maximum Flip-Flops Maximum User I/Os Global Clocks Quadrant Clocks Boundary Scan Testing 3.3V PCI Speed Grades Temperature Grades* Package (by pin count) PQFP TQFP FBGA A54SX08A 8,000 12,000 768 512 256 512 130 3 0 Yes Yes Std A 208 100, 144 144 A54SX16A 16,000 24,000 1,452 924 528 990 180 3 0 Yes Yes Std A 208 100, 144 144, 256 A54SX32A 32,000 48,000 2,880 1,800 1,080 1,980 249 3 0 Yes Yes Std A 208 100, 144 144, 256 A54SX72A 72,000 108,000 6,036 4,024 2,012 4,024 360 3 4 Yes Yes Std A 208 - 256, 484
Note: *The SX-A family is also offered in commercial, industrial and military temperature grades with -F, -1, -2 and -3 speed grades, in addition to the Std speed grade. Refer to the SX-A Family FPGAs datasheet and HiRel SX-A Family FPGAs datasheet for more details.
June 2006 (c) 2006 Actel Corporation
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SX-A Automotive Family FPGAs
Ordering Information
A54SX16A PQ G 208 A Application (Temperature Range) A= Automotive (-40C to 125C) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type FG = Fine Pitch Ball Grid Array (1.0mm pitch) PQ = Plastic Quad Flat Pack TQ = Thin Quad Flat Pack (1.4mm pitch) Part Number A54SX08A = 12,000 System Gates A54SX16A = 24,000 System Gates A54SX32A = 48,000 System Gates A54SX72A = 108,000 System Gates
Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing options available.
Plastic Device Resources
User I/Os (including clock buffers) Device A54SX08A A54SX16A A54SX32A A54SX72A PQFP 208-Pin 130 175 174 171 TQFP 100-Pin 81 81 81 - TQFP 144-Pin 113 113 113 - FBGA 144-Pin 111 111 111 - FBGA 256-Pin - 180 203 203 FBGA 484-Pin - - - 360
Note: Contact your Actel sales representative for product availability. Package Definitions: PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, FBGA = 1.0mm Fine Pitch Ball Grid Array
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Table of Contents
General Description
SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Clock Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 PCI Compliance for the Automotive-Grade SX-A Family . . . . . . . . . . . . . . . . . 1-14 SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38
Package Pin Assignments
208-Pin PQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 100-Pin TQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 144-Pin TQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 144-Pin FBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 256-Pin FBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 484-Pin FBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
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General Description
Actel's SX-A family of FPGAs features a sea-of-modules architecture. SX-A devices simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time-to-market for performance-intensive applications. With the automotive temperature grade support (-40C to 125C), the SX-A devices can address many in-cabin telematics and automobile interconnect applications. Actel's SX-A architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell), each optimized for fast and efficient mapping of synthesized logic functions. The routing and interconnect resources are in the metal layers above the logic modules, providing optimal use of silicon. This enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or "sea-of-modules"), which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX-A devices employ both local and general routing resources. The high-speed local routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (90 percent of connections typically use only three or fewer antifuses). The unique local and general routing structure featured in SX-A devices gives fast and predictable performance, allows 100% pin-locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with minimum effort. Further complementing SX-A's flexible routing structure is a hardwired, constantly loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clockto-out or fast input set-up times. SX-A devices have easyto-use I/O cells that do not require HDL instantiation, facilitating design re-use and reducing design and verification time.
SX-A Family Architecture
Programmable Interconnect Element
The SX-A family provides efficient use of silicon by locating the routing interconnect resources between the top two metal layers (Figure 1-1). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using Actel's patented metal-to-metal programmable antifuse interconnect elements. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The extremely small size of these interconnect elements gives the automotive-grade SX-A devices abundant routing resources and provides excellent protection against design pirating. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and since SX-A is a nonvolatile, single-chip solution, there is no configuration bitstream to intercept. Additionally, the interconnect (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry.
Logic Module Design
The SX-A family architecture is described as a "sea-ofmodules" architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Actel's SX-A family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 1-2 on page 1-3). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the SX-A FPGA. The clock source for the R-cell can be chosen from either the hardwired clock, the routed clocks, or internal logic.
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1-1
Routing Tracks
Amorphous Silicon/ Dielectric Antifuse Metal 4 Tungsten Plug Via
Metal 3 Tungsten Plug Via
Metal 2
Metal 1 Tungsten Plug Contact
Silicon Substrate
Note: A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. A54SX08A, A54SX16A, and A54SX32A have three layers of metal with antifuse between Metal 2 and Metal 3. Figure 1-1 * SX-A Family Interconnect Elements
The C-cell implements a range of combinatorial functions of up to five inputs (Figure 1-3 on page 1-3). Inclusion of the DB input and its associated inverter function allows more than 4,000 combinatorial functions to be implemented in a single module in the SX-A architecture. The inverter function improves flexibility in the architecture; for instance a 3-input exclusive-OR function can be integrated into a single C-cell. At the same time, the C-cell structure is extremely synthesis friendly, simplifying the overall design and reducing synthesis time. Two C cells can be combined together to create a flipflop to imitate an R-cell via the user of the CC macro. This is particularly useful when implementing paths which are not timing-critical or if the designer needs more R-cells. More information about CC macro can be found in Actel's Maximizing Logic Utilization in eX, SX and SX-A FPGA Devices Using CC Macros Application Note.
Chip Architecture
The SX-A family's chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications.
Module Organization
The C-cell and R-cell logic modules are arranged into horizontal groups called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. Clusters are further organized into SuperClusters for even better design efficiency and device performance (Figure 1-4 on page 1-4). SuperCluster 1 is a two-wide grouping of Type 1 Clusters. SuperCluster 2 is a two-wide group containing one Type 1 Cluster and one Type 2 Cluster. SX-A devices feature more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops.
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S0
Routed Data Input S1
PRE DirectConnect Input
D
Q
Y
HCLK CLKA, CLKB, Internal Logic CKS
Figure 1-2 * R-Cell
CLR
CKP
D0 D1 Y D2 D3 Sa Sb
DB A0
Figure 1-3 * C-Cell
B0
A1
B1
Routing Resources
Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 1-5 on page 1-4 and Figure 1-6 on page 1-5). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance.
DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring Rcell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum pin-to-pin propagation time of 0.5 ns.
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R-Cell
C-Cell
Routed S0 Data Input
S1 PRE
D0 D1 Y D2 D Q Y D3 Sa Sb
DirectConnect Input
HCLK CLKA, CLKB, Internal Logic
CLR DB CKS CKP A0 B0 A1 B1
Cluster 1
Cluster 1
Cluster 2
Cluster 1
Type 1 SuperCluster
Figure 1-4 * Cluster Organization
Type 2 SuperCluster
DirectConnect * No antifuses * 0.1 ns maximum routing delay
FastConnect * One antifuse * 0.3 ns maximum routing delay
Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 1 SuperClusters
Figure 1-5 * DirectConnect and FastConnect for Type 1 SuperClusters
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DirectConnect * No antifuses * 0.1 ns maximum routing delay
FastConnect * One antifuse * 0.3 ns maximum routing delay
Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 2 SuperClusters
Figure 1-6 * DirectConnect and FastConnect for Type 2 SuperClusters
In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Actel's segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the fully automatic place-and-route software to minimize signal propagation delays.
Clock Resources
Actel's high-drive routing structure provides three clock networks (Table 1-1). The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. HCLK cannot be connected to combinatorial logic. This provides a fast propagation path for the clock signal, enabling the 5.6 ns clock-to-out (pad-to-pad) performance of the auotmotive-grade SX-A devices. The hardwired clock is tuned to provide clock skew less than 0.3 ns worst case. If not used, this pin must be set as LOW or HIGH on the board. It must not be left floating. Figure 1-7 on page 1-6 describes the clock circuit used for the constant load HCLK. When the device is powered up and TRST is not grounded, HCLK does not function until the fourth clock cycle. This prevents possible false outputs due to a slow power-on-reset signal and fast start-up clock circuit. To activate HCLK from the first cycle, TRST pin must be reserved in the Designer software and the pin must be tied to GND on the board.
Two additional clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the automotive-grade SX-A device. CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB pins are not used or sourced from signals, then these pins must be set as LOW or HIGH on the board. They must not be left floating (except in the A54SX72A where these clocks can be configured as regular I/Os and can float). Figure 1-8 on page 1-6 describes the CLKA and CLKB circuit used in SXA devices with the exception of A54SX72A. In addition to CLKA and CLKB, the A54SX72A device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD - corresponding to bottom-left, bottom-right, top-left, and top-right locations on the die, respectively), which can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. If QCLKs are not used as quadrant clocks, they will behave as regular I/Os. Bidirectional clock buffers are also available on the A54SX72A. The CLKA, CLKB, and QCLK circuits for A54SX72A are shown in Figure 1-9 on page 16. Note that bidirectional clock buffers are only available in A54SX72A. For more information, refer to the "Pin Description" on page 1-38. For more information on how to use quadrant clocks in the A54SX72A device, refer to the Global Clock Networks in Actel's Antifuse Devices and Using A54SX72A and RT54SX72S Quadrant Clocks application notes.
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Table 1-1 * SX-A Clock Resources A54SX08A Routed Clocks (CLKA, CLKB) Hardwired Clocks (HCLK) Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD) 2 1 0 A54SX16A 2 1 0 A54SX32A 2 1 0 A54SX72A 2 1 4
Constant Load Clock Network HCLKBUF
Figure 1-7 * SX-A HCLK Clock Pad
Clock Network
From Internal Logic
CLKBUF CLKBUFI CLKINT CLKINTI
Figure 1-8 * SX-A Routed Clock Structure Except for A54SX72A
OE From Internal Logic To Internal Logic
Clock Network
From Internal Logic CLKBUF CLKBUFI CLKINT CLKINTI CLKBIBUF CLKBIBUFI QCLKBUF QCLKBUFI QCLKINT QCLKINTI QCLKBIBUF QCLKBIBUFI
Figure 1-9 * A54SX72A Routed Clock and QClock Structure
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Other Architectural Features
Technology
The automotive-grade SX-A devices are implemented on a high-voltage, twin-well CMOS process using 0.22 design rules. The metal-to-metal antifuse is comprised of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ("on" state) resistance of 25 with capacitance of 1.0 fF for low signal impedance.
I/O Modules
Each user I/O on an automotive-grade SX-A device can be configured as an input, an output, a tristate output, or a bidirectional pin. I/O pins can be set for 2.5 V or 3.3 V operation through VCCI. SX-A I/Os, combined with array registers, can achieve clock-to-output-pad timing of 5.6 ns even without the dedicated I/O registers. In most FPGAs, I/O cells that have embedded latches and flipflops require instantiation in HDL code; this is a design complication not encountered in SX-A FPGAs. Fast pinto-pin timing ensures that the device is able to interface with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. All unused I/Os are configured as tristate outputs by Actel's Designer software, for maximum flexibility when designing new boards or migrating existing designs. SX-A inputs should be driven by high-speed push-pull devices with a low-resistance pull-up device. If the input voltage is greater than VCCI and a fast push-pull device is NOT used, the high-resistance pull-up of the driver and the internal circuitry of the SX-A I/O may create a voltage divider. This voltage divider could pull the input voltage below specification for some devices connected to the driver. A logic '1' may not be correctly presented in this case. For example, if an open drain driver is used with a pull-up resistor to 3.3V to provide the logic '1' input, and VCCI is set to 2.5 V on the SX-A device, the input signal may be pulled down by the SX-A input. Each I/O module has an available power-up resistor of approximately 50 k that can configure the I/O in a known state during power-up. Just slightly before VCCA reaches 2.5 V, the resistors are disabled, so the I/Os will be controlled by user logic. See Table 1-2 on page 1-8 and Table 1-3 on page 1-8 for more information concerning available I/O features.
Performance
The combination of architectural features described above enables automotive-grade SX-A devices to operate with internal clock frequencies of 250 MHz, enabling fast execution of even complex logic functions at extended tempetature ranges. Thus, the automotivegrade SX-A devices are an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can be integrated into an SX-A device with dramatic improvements in cost and time-to-market. Using timing-driven place-and-route tools, designers can achieve highly deterministic device performance.
User Security
The Actel FuseLock advantage ensures that unauthorized users will not be able to read back the contents of an Actel antifuse FPGA. In addition to the inherent strengths of the architecture, special security fuses that prevent internal probing and overwriting are hidden throughout the fabric of the device. They are located such that they cannot be accessed or bypassed without destroying the rest of the device, making both invasive and more-subtle noninvasive attacks ineffective against Actel antifuse FPGAs. Look for this symbol to ensure your valuable IP is secure.
Hot Swapping
During power-up/down (or partial up/down), all I/Os are tristated. VCCA and VCCI do not have to be stable during power-up/down. After the SX-A device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The device's output pins are driven to a high impedance state until normal chip operating conditions are reached. Table 1-4 on page 1-8 summarizes the VCCA voltage at which the I/Os behave according to the user's design for an SX-A device at room temperature for various ramp-up rates. The data reported assumes a linear ramp-up profile to 2.5V. For more information on power-up and hot-swapping, refer to the application note, Actel SX-A and RT54SX-S Devices in Hot-Swap and Cold-Sparing Applications.
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For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note.
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Table 1-2 * I/O Features Function Input Buffer Threshold Selections Flexible Output Driver Output Buffer Description * * * * * * 3.3V PCI, LVTTL 2.5V LVCMOS2 3.3V PCI, LVTTL 2.5V LVCMOS2 I/O on an unpowered device does not sink current Can be used for "cold-sparing"
"Hot-Swap" Capability (except 3.3V PCI)
Selectable on an individual I/O basis Individually selectable slew rate, high slew or low slew (The default is high slew rate). The slew is only affected on the falling edge of an output. Rising edges of outputs are not affected. Power-Up Individually selectable pull-ups and pull-downs during power-up (default is to power-up in tristate) Enables deterministic power-up of device VCCA and VCCI can be powered in any order Table 1-3 * I/O Characteristics for All I/O Configurations Hot Swappable LVTTL, LVCMOS2 3.3V PCI Yes No Slew Rate Control Yes. Only affects falling edges of outputs No. High slew rate only Power-Up Resistor Pull-up or pull-down Pull-up or pull-down
Table 1-4 * Power-up Time at which I/Os Become Active Supply Ramp Rate Units A54SX08A A54SX16A A54SX32A A54SX72A 0.25V/s s 10 10 10 10 0.025V/s s 96 100 100 100 5V/ms ms 0.34 0.36 0.46 0.41 2.5V/ms ms 0.65 0.62 0.74 0.67 0.5V/ms ms 2.7 2.5 2.8 2.6 0.25V/ms ms 5.4 4.7 5.2 5.0 0.1V/ms ms 12.9 11.0 12.1 12.1 0.025V/ms ms 50.8 41.6 47.2 47.2
Boundary-Scan Testing (BST)
Automotive-grade SX-A devices are IEEE 1149.1 compliant and offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. The BST function is controlled through the special JTAG pins (TMS, TDI, TCK, TDO, and TRST). The functionality of the JTAG pins is defined by two available modes: Dedicated and Flexible. TMS cannot be employed as user I/O in either mode.
To select Dedicated mode, users need to reserve the JTAG pins in Actel's Designer software. To reserve the JTAG pins, users can check the "Reserve JTAG" box in "Device Selection Wizard" (Figure 1-10 on page 1-9). To select Dedicated mode, users need to reserve the JTAG pins in Actel's Designer software by checking the "Reserve JTAG" box in "Device Selection Wizard" (Figure 1-10 on page 1-9). JTAG pins comply with LVTTL/ TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. Refer to the "3.3V LVTTL Electrical Specifications" on page 1-13 and "2.5V LVCMOS2 Electrical Specifications" on page 1-14 for detailed specifications.
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST; designers cannot use them as regular I/Os. An internal pull-up resistor is automatically enabled on both TMS and TDI pins, and the TMS pin will function as defined in the IEEE 1149.1 (JTAG) specification.
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Upon power-up, the TAP controller enters the Test-LogicReset state. In this state, TDI, TCK and TDO function as user I/Os. The TDI, TCK, and TDO are transformed from user I/Os into BST pins when a rising edge on TCK is detected while TMS is at logic low. To return to TestLogic Reset state, TMS must be high for at least five TCK cycles. An external 10K pull-up resistor to VCCI should be placed on the TMS pin to pull it HIGH by default. Table 1-5 describes the different configuration requirements of BST pins and their functionality in different modes.
Figure 1-10 * Device Selection Wizard
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan Reset pin when the "Reserve JTAG Test Reset" option is selected as shown in Figure 1-10 on page 1-9. An internal pull-up resistor is permanently enabled on the TRST pin in this mode. Actel recommends connecting this pin to ground in normal operation to keep the JTAG state controller in the Test-Logic-Reset state. When JTAG is being used, it can be left floating or be driven high. When the "Reserve JTAG Test Reset" option is not selected, this pin will function as a regular I/O. If unused as an I/O in the design, it will be configured as a tristated output.
TAP Controller State Any Test-Logic-Reset Any EXCEPT Test-Logic-Reset
Flexible Mode
In Flexible mode, TDI, TCK, and TDO may be employed as either user I/Os or as JTAG input pins. The internal resistors on the TMS and TDI pins are not present in flexible JTAG mode. To select the Flexible mode, users need to uncheck the "Reserve JTAG" box in "Device Selection Wizard" in Actel's Designer software. In Flexible mode, TDI, TCK and TDO pins may function as user I/Os or BST pins. The functionality is controlled by the BST TAP controller. The TAP controller receives two control inputs, TMS and TCK.
Table 1-5 * Boundary-Scan Pin Configurations and Functions Mode Dedicated (JTAG) Flexible (User I/O) Flexible (JTAG)
Designer "Reserve JTAG" Selection Checked Unchecked Unchecked
Probing Capabilities
Automotive-grade SX-A devices also provide an internal probing capability that is accessed with the JTAG pins. The Silicon Explorer II Diagnostic Hardware is used to control the TDI, TCK, TMS and TDO pins to select the desired nets for debugging. The user assigns the selected internal nets in Actel's Silicon Explorer II software to the PRA/PRB output pins for observation. Silicon Explorer II automatically places the device into JTAG mode. However, probing functionality is only activated when the TRST pin is driven high or left floating, allowing the internal pull-up resistor to pull TRST to HIGH. If the TRST pin is held LOW, the TAP controller remains in the TestLogic-Reset state so no probing can be performed. However, the user must drive the TRST pin HIGH or allow the internal pull-up resistor to pull TRST HIGH. When selecting the "Reserve Probe Pin" box as shown in Figure 1-10 on page 1-9, direct the layout tool to reserve the PRA and PRB pins as dedicated outputs for probing. This "reserve" option is merely a guideline. If the designer assigns user I/Os to the PRA and PRB pins and selects the "Reserve Probe Pin" option, Designer Layout will override the "Reserve Probe Pin" option and place the user I/Os on those pins. To allow probing capabilities, the security fuse must not be programmed. Programming the security fuse disables the probe circuitry. Table 1-6 on page 1-10 summarizes the possible device configurations for probing once the device leaves the "Test-Logic-Reset" JTAG state.
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1-9
Table 1-6 * Device Configuration Options for Probe Capability (TRST pin reserved) JTAG Mode Dedicated Flexible Dedicated Flexible - Note: 1. If the TRST pin is not reserved, the device behaves according to TRST=HIGH as described in the table. 2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input signals will not pass through these pins and may cause contention. 3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by the Designer software. TRST1 LOW LOW HIGH HIGH - Security Fuse Programmed No No No No Yes PRA, PRB2 User I/O3 User I/O3 TDI, TCK, TDO2 Probing Unavailable User I/O3 Probe Circuit Inputs Probe Circuit Inputs Probe Circuit Secured
Probe Circuit Outputs Probe Circuit Outputs Probe Circuit Secured
SX-A Probe Circuit Control Pins
Automotive-grade SX-A devices contain internal probing circuitry that provides built-in access to every node in a design, enabling 100% real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy-to-use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18 channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. The Silicon Explorer II tool uses the boundary-scan ports (TDI, TCK, TMS, and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 1-11 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification
16 Pin Connection TDI TCK
SX-A FPGAs
Serial Connection
Silicon Explorer II
TMS TDO PRA PRB
22 Pin Connection
Additional 16 Channels (Logic Analyzer)
Figure 1-11 * Probe Setup
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v2.2
Design Considerations
Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, critical input signals through these pins are not available. In addition, do not program the Security Fuse. Programming the Security Fuse disables the Probe Circuit. Actel recommends that you use a 70 series termination resistor on every probe connector (TDI, TCK, TMS, TDO, PRA, PRB). The 70 series termination, effective for traces of fewer than 8 inches, is used to prevent data transmission corruption during probing and reading back the checksum.
Programming
Device programming is supported through Silicon Sculptor series of programmers. In particular, Silicon Sculptor is compact, robust, single-site and multi-site device programmer for the PC. With standalone software, Silicon Sculptor allows concurrent programming of multiple units from the same PC, ensuring the fastest programming times possible. Each fuse is subsequently verified by Silicon Sculptor II to insure correct programming. In addition, integrity tests ensure that no extra fuses are programmed. Silicon Sculptor also provides extensive hardware self-testing capability. The procedure for programming an SX-A Automotive device using Silicon Sculptor is as follows: 1. Load the .AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via in-house programming from the factory. For detailed information on programming, read the following documents Programming Antifuse Devices and Silicon Sculptor User's Guide.
Development Tool Support
The SX-A Automotive family of FPGAs is fully supported by both Actel's Libero(R) Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is a design management environment that streamlines the design flow. Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify(R) for Actel from Synplicity(R), ViewDraw(R) for Actel from Mentor Graphics(R), ModelSimTM HDL Simulator from Mentor Graphics, WaveFormer LiteTM from SynaptiCADTM, and Designer software from Actel. Refer to the Libero IDE flow (located on Actel's website) diagram for more information. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can lock his/her design pins before layout while minimally impacting the results of place-and-route. Additionally, the backannotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel's integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.
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Related Documents
Application Notes
Global Clock Networks in Actel's Antifuse Devices http://www.actel.com/documents/GlobalClk_AN.pdf Using A54SX72A and RT54SX72S Quadrant Clocks http://www.actel.com/documents/QCLK_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/ Antifuse_Security_AN.pdf Actel eX, SX-A, and RTSX-S I/Os http://www.actel.com/documents/AntifuseIO_AN.pdf Actel SX-A and RT54SX-S Devices in Hot-Swap and ColdSparing Applications http://www.actel.com/documents/ HotSwapColdSparing_AN.pdf Programming Antifuse Devices http://www.actel.com/documents/ AntifuseProgram_AN.pdf
Datasheets
SX-A Family FPGAs http://www.actel.com/documents/SXA_DS.pdf HiRel SX-A Family FPGAs http://www.actel.com/documents/HRSXA_DS.pdf
User's Guides
Silicon Sculptor User's Guide http://www.actel.com/documents/SiliSculptII_WIN_ug.pdf
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Operating Conditions
Table 1-7 * Absolute Maximum Ratings1 Symbol VCCI VCCA VI VO TSTG Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. 2. SX-A Automotive devices are not 5 V tolerant. Table 1-8 * Recommended Operating Conditions Parameter Temperature Range2 Automotive1 -40 to +125 2.375 to 2.625 3.135 to 3.465 Units C V V Parameter DC Supply Voltage for I/Os DC Supply Voltage for Array Input Voltage Output Voltage Storage Temperature Limits -0.3 to +4.0 -0.3 to +3.0 -0.5 to VCCI +0.5 -0.5 to +VCCI -65 to +150 Units V V V V C
2.5V Power Supply Range 3.3V Power Supply Range Notes:
1. Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing options available. 2. Ambient temperature (TA).
3.3V LVTTL Electrical Specifications
Automotive Symbol VOH VOL VIL VIH IIL / IIH IOZ tR, tF1,2 CIO ICC3 IV Curve Note: 1. 2. 3. tR is the transition time from 0.7V to 2.1V. tF is he transition time from 2.1V to 0.7V. ICC = ICCI + ICCA VCCI = MIN, VI = VIH or VIL VCCI = MIN, VI = VIH or VIL Input Low Voltage Input High Voltage Input Leakage Current, VIN = VCCI or GND 3-State Output Leakage Current Input Transition Time tR, tF I/O Capacitance Standby Current Can be derived from the IBIS model at http://www.actel.com/techdocs/models/ibis.html. 2.1 -20 -20 20 20 10 10 45 Parameter IOH = -2mA IOL = 2mA Min 2.4 0.4 0.7 Max V V V V A A ns pF mA Units
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1-13
2.5V LVCMOS2 Electrical Specifications
Automotive Symbol VOH VOL VIL VIH IIL / IIH IOZ tR, tF CIO ICC3 IV Curve Note: 1. 2. 3. tR is the transition time from 0.6V to 1.7V. tF is he transition time from 1.7V to 0.6V. ICC = ICCI + ICCA
1,2
Parameter VCCI = MIN, VI = VIH or VIL VCCI = MIN, VI = VIH or VIL Input Low Voltage, VOUT =< VVOL (max) Input High Voltage, VOUT >= VVOH (min) Input Leakage Current, VIN = VCCI or GND 3-State Output Leakage Current Input Transition Time tR, tF I/O Capacitance Standby Current IOH = -1mA IOL = 1mA
Min. 1.8
Max.
Units V
0.5 0.6 1.7 -20 -20 20 20 10 10 35
V V V A A ns pF mA
Can be derived from the IBIS model at http://www.actel.com/techdocs/models/ibis.html.
PCI Compliance for the Automotive-Grade SX-A Family
The automotive-grade SX-A devices support 3.3V PCI and are compliant with the PCI Local Bus Specification Rev. 2.1.
Table 1-9 * DC Specifications (3.3V PCI Operation) Symbol VCCA VCCI VIH VIL IIPU IIL VOH VOL CIN CCLK Note: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Designers should ensure that the input buffer is conducting minimum current at this input voltage in applications sensitive to static power utilization. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). Parameter Supply Voltage for Array Supply Voltage for I/Os Input High Voltage Input Low Voltage Input Pull-up Voltage1 Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance3 CLK Pin Capacitance 5
2
Condition
Min. 2.375 3.135 0.5VCCI -0.5 0.7VCCI
Max. 2.625 3.465 VCCI + 0.5 0.3VCCI
Units V V V V V
0 < VIN < VCCI IOUT = -500 A IOUT = 1500 A
-20 0.9VCCI
+20
A V
0.1VCCI 10 12
V pF pF
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Table 1-10 * AC Specifications (3.3V PCI Operation) Symbol IOH(AC) Parameter Switching Current High Condition 0 < VOUT 0.3VCCI
1
Min. -12VCCI (-17.1(VCCI - VOUT))
1, 2
Max.
Units mA mA
0.3VCCI VOUT < 0.9VCCI 1 0.7VCCI < VOUT < VCCI (Test Point) IOL(AC) Switching Current Low VOUT = 0.7VCC 2 VCCI > VOUT 0.6VCCI
1 1
EQ 1-1 on page 1-17 -32VCCI 16VCCI (26.7VOUT) EQ 1-2 on page 1-17 38VCCI -25 + (VIN + 1)/0.015 25 + (VIN - VCCI - 1)/0.015 1 1 4 4 mA mA mA V/ns V/ns mA mA mA
0.6VCCI > VOUT > 0.1VCCI 0.18VCCI > VOUT > 0 1, 2 (Test Point) ICL ICH slewR slewF Note: Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.18VCC 2 -3 < VIN -1 VCCI + 4 > VIN VCCI + 1 0.2VCCI - 0.6VCCI load
3
0.6VCCI - 0.2VCCI load 3
1. Refer to the V/I curves in Figure 1-12 on page 1-16. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D) are provided with the respective diagrams in Figure 1-12 on page 1-16. The equation defined maximum should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs.
pin output buffer 1k/25 1/2 in. max. 10 pF
pin output buffer
1k/25 10 pF
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1-15
Figure 1-12 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the automotivegrade SX-A devices.
150.0 IOL MAX Spec 100.0 50.0 0.0 0 -50.0 -100.0 -150.0 Voltage Out (V) 0.5 IOH MIN Spec IOH IOH MAX Spec 1 1.5 2 2.5 3 3.5 4 IOL
Figure 1-12 * 3.3V PCI V/I Curve for Automotive-Grade SX-A Devices
Equation C IOH = (98.0/VCCI ) (VOUT - VCCI ) (VOUT + 0.4VCCI )
for 0.7 VCCI < VOUT < VCCI
Equation D IOL = (256/VCCI ) VOUT (VCCI - VOUT )
for 0V < VOUT < 0.18 VCCI
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Current (mA)
IOL MIN Spec
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Junction Temperature (TJ)
The temperature variable in the Designer Series software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. Equation 1, shown below, can be used to calculate junction temperature. Junction Temperature = T + Ta +
EQ 1-1
Where: Ta = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P
EQ 1-2
P = Power
ja = Junction to ambient of package. ja numbers are
located in the Package Thermal Characteristics table below.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. The maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a TQFP 144-pin package at automotive temperature and still air is as follows:
Max. junction temp. (C) - Max. ambient temp. (C) 150C - 125C Maximum Power Allowed = -------------------------------------------------------------------------------------------------------------------------------------- = --------------------------------------- = 0.78W ja (C/W) 32C/W Table 1-11 * Package Thermal Characteristics Package Type Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) Plastic Quad Flat Pack (PQFP)
1 2
Pin Count 100 144 208 208 144 256 484
jc 12 11 8 3.8 3.8 3.3 3
ja Still Air 37.5 32 30 20 38.8 30 20
ja 300 ft/min 30 24 23 17 26.7 25 15
Units C/W C/W C/W C/W C/W C/W C/W
Plastic Quad Flat Pack (PQFP) with Heat Spreader Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Note:
1. The A54SX08A PQ208 has no heat spreader. 2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A.
For Power Estimator information, please go to http://www.actel.com/products/tools/index.html.
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SX-A Timing Model*
Input Delays Internal Delays Combinatorial Cell Predicted Routing Delays Output Delays
I/O Module tINYH = 1.0 ns
tIRD1 = 0.5 ns tIRD2 = 0.7 ns
I/O Module
tPD = 1.5 ns
tRD1 = 0.6 ns tRD4 = 1.1 ns tRD8 = 2.0 ns I/O Module tDHL = 3.8 ns
tDHL = 3.8 ns
Register Cell
tSUD = 1.2 ns tHD = 0.0 ns Routed Clock
D
Q
tRD1 = 0.6 ns tENZL = 2.8 ns
tRCKH = 2.2 ns (100% Load)
tRCO = 1.0 ns Register Cell
I/O Module tDHL = 3.8 ns
I/O Module tINYH = 1.0 ns tSUD = 1.2 ns tHD = 0.0 ns Hard-Wired Clock
D
Q
tRD1 = 0.6 ns tENZL = 2.8 ns
tHCKH = 1.8 ns
tRCO = 1.0 ns
Note: *Values shown for A54SX08A, worst-case automotive conditions at 3.3V PCI with standard place-and-route. Figure 1-13 * Timing Model
Sample Path Calculations
Hardwired Clock External Setup =(tINYH + tIRD2 + tSUD) - tHCKH =1.0+0.7+1.2-1.8=1.1ns Clock-to-Out (Pad-to-Pad) =tHCKH + tRCO + tRD1 + tDHL =1.8+1.0+0.6+3.8=7.2ns Routed Clock External Setup = (tINYH + tIRD2 + tSUD) - tRCKH = 1.0+0.7+1.2-1.8=1.1ns Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tDHL = 1.8+1.0+0.6+3.8=7.2ns
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Output Buffer Delays
E D TRIBUFF PAD To AC test loads (shown below)
VCC In Out VOL tDLH 50% 50% VOH 1.5V tDHL GND 1.5V En Out
VCC 50% 50% VCC 1.5V VOL t ENZL tENLZ GND 10% E Out GND
VCC 50% 50% VOH 1.5V tENZH tENHZ GND 90%
Figure 1-14 * Output Buffer Delay
Load 1 (Used to measure propagation delay) To the output under test 35 pF
Load 2 (Used to measure enable delays) VCC GND
Load 3 (Used to measure disable delays) VCC GND
To the output under test
R to VCC for t PZL R to GND for t PZH R = 1 k
To the output under test
R to VCC for t PLZ R to GND for t PHZ R = 1 k
35 pF
5 pF
Figure 1-15 * AC Test Loads
PAD
INBUF
Y VCC S, A or B 50% 50% VCC 50% tPD 50% t PD
S A B
Y
GND 50% t PD GND tPD VCC 50%
In Out GND
3V 1.5V 1.5V VCC 50%
0V 50%
Out GND Out
Figure 1-16 * Input Buffer Delays
Figure 1-17 * C-Cell Delays
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1-19
Cell Timing Characteristics
D CLK
PRESET CLR
Q
(Positive Edge-Triggered) t HD D t SUD CLK t HPWH t RPWH t RCO Q t CLR CLR t WASYN PRESET
Figure 1-18 * Cell Timing Characteristics
tHP t t HPWL RPWL
t PRESET
Timing Characteristics
Timing characteristics for SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all SX-A family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with postlayout delays.
Long Tracks
Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout routing delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6 percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical.
Timing Derating
SX-A devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing.
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Table 1-12 * Temperature and Voltage Derating Factors (Normalized to TJ = 125C, VCCA = 2.3 V) Junction Temperature (TJ) VCCA 2.3 V 2.5 V 2.7 V -55C 0.7 0.65 0.66 -40C 0.70 0.66 0.62 0C 0.77 0.72 0.67 25C 0.78 0.73 0.69 70C 0.88 0.83 0.78 85C 0.91 0.85 0.80 125C 1.00 0.93 0.88
Table 1-13 * A54SX08A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C) `Std' Speed Parameter tPD tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN tINYH tINYL Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance. Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Hold Time Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW 1.2 0.0 2.3 0.6 0.5 1.0 1.6 1.0 1.2 1.2 ns ns ns ns ns ns ns ns ns ns Description
1
Min.
Max. 1.5 0.1 0.5 0.6 0.7 0.9 1.1 2.0 2.9
Units ns ns ns ns ns ns ns ns ns
C-Cell Propagation Delays Predicted Routing Delays
Internal Array Module
2
FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
Input Module Propagation Delays
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Table 1-13 * A54SX08A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C) (Continued) `Std' Speed Parameter tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance. Description
2
Min.
Max. 0.5 0.7 0.9 1.1 2.0 2.9 2.1
Units ns ns ns ns ns ns
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input)
Dedicated (Hardwired) Array Clock Networks ns 1.8 ns 2.4 2.4 0.3 4.8 208 1.8 ns 2.2 ns 2.2 ns 2.5 ns 2.3 ns 2.6 ns 2.4 2.4 0.3 0.5 0.5 ns ns ns ns ns ns ns ns ns MHz
Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
Routed Array Clock Networks
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Table 1-13 * A54SX08A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C) (Continued) `Std' Speed Parameter tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW tDLH tDHL tDHLS tENZL tENZLS Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance. Description Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load)
3
Min. 1.8
Max.
Units
Dedicated (Hardwired) Array Clock Networks ns 1.7 ns 2.4 2.4 0.3 4.8 208 1.8 ns 2.3 ns 2.1 ns 2.5 ns 2.2 ns 2.6 ns 2.4 2.4 0.5 0.5 0.5 5.0 21.8 4.6 22.8 6.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Routed Array Clock Networks
2.5 V LVTTL Output Module Timing
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--low slew Enable-to-Pad, Z to L Data-to-Pad, Z to L--low slew
v2.2
1-23
Table 1-13 * A54SX08A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C) (Continued) `Std' Speed Parameter tENZH tENLZ tENHZ dTLH dTHL dTHLS tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance. Description Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW Delta HIGH to LOW--low slew
4
Min.
Max. 4.1 6.7 0.064 0.029 0.108 5.0
Units ns ns ns ns/pF ns/pF ns/pF ns
3.3 V PCI Output Module Timing
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW Delta HIGH to LOW--low slew
3.8 3.8 2.8 2.8 4.8 4.8 0.050 0.019 5.3 4.8 17.3 4.3 31.9 5.5 5.5 4.8 0.050 0.019 0.092
ns ns ns ns ns ns/pF ns/pF ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
3.3 V LVTTL Output Module Timing3
1 -2 4
v2.2
Table 1-14 * A54SX16A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125C) `Std' Speed Parameter C-Cell Propagation tPD Predicted Routing tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time 1.2 0.0 2.3 0.6 0.5 1.0 1.2 1.2 ns ns ns ns ns ns ns ns Description Delays1 Internal Array Module Delays2 FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.5 0.6 0.7 0.9 1.1 2.0 2.9 ns ns ns ns ns ns ns ns 1.5 ns Min Max. Units
Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW Delays2 0.5 0.7 0.9 1.1 0.9 2.9 ns ns ns ns ns ns 1.0 1.6 ns ns
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes:
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
v2.2
1-25
Table 1-14 * A54SX16A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125C) (Continued) `Std' Speed Parameter Description Min Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 4.8 208 2.4 2.4 0.1 2.2 ns 2.1 ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.4 2.4 0.5 0.9 0.9 2.1 ns 2.2 ns 2.6 ns 2.4 ns 2.6 ns 3.1 ns ns ns ns ns ns
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance. Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) 2.2 ns 2.1 ns
1 -2 6
v2.2
Table 1-14 * A54SX16A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125C) (Continued) `Std' Speed Parameter tHPWH tHPWL tHCKSW tHP fHMAX Description Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 4.8 208 Min 2.4 2.4 0.1 Max. Units ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Timing3 6.3 5.0 21.8 4.6 22.8 6.7 4.1 6.7 ns ns ns ns ns ns ns ns 2.4 2.4 0.5 0.9 0.9 2.1 ns 2.3 ns 2.6 ns 2.7 ns 3.0 ns 3.1 ns ns ns ns ns ns
2.5 V LVTTL Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ Notes:
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--low slew Enable-to-Pad, Z to L Data-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
v2.2
1-27
Table 1-14 * A54SX16A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125C) (Continued) `Std' Speed Parameter dTLH dTHL dTHLS Description Delta LOW to HIGH Delta HIGH to LOW Delta HIGH to LOW--low slew
4
Min
Max. 0.064 0.029 0.108
Units ns/pF ns/pF ns/pF
3.3 V PCI Output Module Timing tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW
3
3.8 3.8 2.8 2.8 4.8 4.8 0.050 0.019
ns ns ns ns ns ns ns/pF ns/pF
3.3 V LVTTL Output Module Timing tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Notes:
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW Delta HIGH to LOW--low slew
5.3 4.8 17.3 4.3 31.9 5.5 5.5 4.8 0.050 0.019 0.092
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
1 -2 8
v2.2
Table 1-15 * A54SX32A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C `Std' Speed Parameter C-Cell Propagation tPD Predicted Routing tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time 1.2 0.0 2.3 0.6 0.5 1.0 1.2 1.2 ns ns ns ns ns ns ns ns Description Delays1 Internal Array Module Delays2 FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.5 0.6 0.7 0.9 1.1 2.0 2.9 ns ns ns ns ns ns ns ns 1.5 ns Min. Max. Units
Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW Delays2 0.5 0.7 ns ns 1.0 1.6 ns ns
Input Module Predicted Routing tIRD1 tIRD2 Notes:
FO=1 Routing Delay FO=2 Routing Delay
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
v2.2
1-29
Table 1-15 * A54SX32A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C (Continued) `Std' Speed Parameter tIRD3 tIRD4 tIRD8 tIRD12 Description FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay Min. Max. 0.9 1.1 2.0 2.9 Units ns ns ns ns
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 5.0 199 2.5 2.5 0.6 3.1 2.6 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance. Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.5 2.5 1.5 2.2 2.3 3.0 3.7 3.7 3.9 4.3 4.3 ns ns ns ns ns ns ns ns ns ns ns
1 -3 0
v2.2
Table 1-15 * A54SX32A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C (Continued) `Std' Speed Parameter Description Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 5.0 199 2.5 2.5 0.6 3.1 2.6 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 2.5 2.5 1.5 2.2 2.3 3.0 3.7 3.7 3.9 4.3 4.3 ns ns ns ns ns ns ns ns ns ns ns
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance. Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) 3.1 2.6 ns ns
v2.2
1-31
Table 1-15 * A54SX32A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C (Continued) `Std' Speed Parameter tHPWH tHPWL tHCKSW tHP fHMAX Description Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 5.0 199 Min. 2.5 2.5 0.6 Max. 0.0 Units ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Timing3 6.3 5.0 21.8 4.6 22.8 6.7 4.1 6.7 ns ns ns ns ns ns ns ns 2.5 2.5 1.5 2.2 2.3 3.0 3.8 3.7 3.9 4.3 4.3 ns ns ns ns ns ns ns ns ns ns ns
2.5 V LVTTL Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ Notes:
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--low slew Enable-to-Pad, Z to L Data-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
1 -3 2
v2.2
Table 1-15 * A54SX32A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C (Continued) `Std' Speed Parameter dTLH dTHL dTHLS Description Delta LOW to HIGH Delta HIGH to LOW Delta HIGH to LOW--low slew
4
Min.
Max. 0.064 0.029 0.108
Units ns/pF ns/pF ns/pF
3.3 V PCI Output Module Timing tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW
3
3.8 3.8 2.8 2.8 4.8 4.8 0.050 0.019
ns ns ns ns ns ns ns/pF ns/pF
3.3 V LVTTL Output Module Timing tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Notes:
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW Delta HIGH to LOW--low slew
5.3 4.8 17.3 4.3 31.9 5.5 5.5 4.8 0.050 0.019
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
v2.2
1-33
Table 1-16 * A54SX72A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C) `Std' Speed Parameter C-Cell Propagation tPD Predicted Routing tDC tFC tRD1 tRD2 tRD3 tRD4 tRD8 tRD12 R-Cell Timing tRCO tCLR tPRESET tSUD tHD tWASYN tRECASYN tHASYN Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Data Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Hold Time 1.2 0.0 2.3 0.6 0.5 1.0 1.2 1.2 ns ns ns ns ns ns ns ns Description Delays1 Internal Array Module Delays2 FO=1 Routing Delay, Direct Connect FO=1 Routing Delay, Fast Connect FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay 0.1 0.5 0.6 0.8 1.0 1.2 2.4 3.4 ns ns ns ns ns ns ns ns 1.5 ns Min. Max. Units
Input Module Propagation Delays tINYH tINYL Input Data Pad-to-Y HIGH Input Data Pad-to-Y LOW Delays2 0.6 0.8 1.0 1.2 2.4 3.4 ns ns ns ns ns ns 1.0 1.6 ns ns
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tIRD12 Notes:
FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay FO=12 Routing Delay
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
1 -3 4
v2.2
Table 1-16 * A54SX72A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C) (Continued) `Std' Speed Parameter Description Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 5.0 199 2.5 2.5 1.1 2.4 2.2 ns ns ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) 6.9 6.5 5.6 5.3 4.6 4.0 ns ns ns ns ns ns ns ns ns ns ns
Dedicated (Hardwired) Array Clock Networks tHCKH tHCKL Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance. Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) 2.4 2.2 ns ns
v2.2
1-35
Table 1-16 * A54SX72A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C) (Continued) `Std' Speed Parameter tHPWH tHPWL tHCKSW tHP fHMAX Description Minimum Pulse Width HIGH Minimum Pulse Width LOW Maximum Skew Minimum Period Maximum Frequency 5.0 199 Min. 2.5 2.5 1.1 Max. Units ns ns ns ns MHz
Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH tRPWL tRCKSW tRCKSW tRCKSW Input LOW to HIGH (Light Load) (Pad to R-Cell Input) Input HIGH to LOW (Light Load) (Pad to R-Cell Input) Input LOW to HIGH (50% Load) (Pad to R-Cell Input) Input HIGH to LOW (50% Load) (Pad to R-Cell Input) Input LOW to HIGH (100% Load) (Pad to R-Cell Input) Input HIGH to LOW (100% Load) (Pad to R-Cell Input) Min. Pulse Width HIGH Min. Pulse Width LOW Maximum Skew (Light Load) Maximum Skew (50% Load) Maximum Skew (100% Load) Timing3 6.5 5.0 22.6 4.6 22.8 6.7 4.1 6.7 ns ns ns ns ns ns ns ns 6.9 6.5 5.6 5.3 4.7 4.0 ns ns ns ns ns ns ns ns ns ns ns
2.5 V LVTTL Output Module tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ Notes:
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--low slew Enable-to-Pad, Z to L Data-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
1 -3 6
v2.2
Table 1-16 * A54SX72A Timing Characteristics (Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125C) (Continued) `Std' Speed Parameter dTLH dTHL dTHLS Description Delta LOW to HIGH Delta HIGH to LOW Delta HIGH to LOW--low slew
4
Min.
Max. 0.064 0.029 0.108
Units ns/pF ns/pF ns/pF
3.3 V PCI Output Module Timing tDLH tDHL tENZL tENZH tENLZ tENHZ dTLH dTHL
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Enable-to-Pad, Z to L Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW
3
3.8 3.8 2.8 2.8 4.8 4.8 0.050 0.019
ns ns ns ns ns ns ns/pF ns/pF
3.3 V LVTTL Output Module Timing tDLH tDHL tDHLS tENZL tENZLS tENZH tENLZ tENHZ dTLH dTHL dTHLS Notes:
Data-to-Pad LOW to HIGH Data-to-Pad HIGH to LOW Data-to-Pad HIGH to LOW--low slew Enable-to-Pad, Z to L Enable-to-Pad, Z to L--low slew Enable-to-Pad, Z to H Enable-to-Pad, L to Z Enable-to-Pad, H to Z Delta LOW to HIGH Delta HIGH to LOW Delta HIGH to LOW--low slew
5.3 4.8 17.3 4.3 31.9 5.5 5.5 4.8 0.050 0.019 0.092
ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual performance. 3. Delays based on 35 pF loading. 4. Delays based on 10 pF loading and 25 resistance.
v2.2
1-37
Pin Description
CLKA/B Clock A and B
TCK, I/O
Test Clock
These pins are clock inputs for clock distribution networks. Input levels are compatible with standard LVTTL or 3.3 V PCI specifications. The clock input is buffered prior to clocking the R-cells. If not used, these pins must be set LOW or HIGH on the board except A54SX72A. In A54SX72A these clocks can be configured as user I/O.
QCLKA/B/C/D, Quadrant Clock A, B, C, and D I/O
Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 1-5 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDI, I/O Test Data Input
These four pins are the quadrant clock inputs and are only for A54SX72A with A, B, C and D corresponding to bottom-left, bottom-right, top-left and top-right quadrants, respectively. They are clock inputs for clock distribution networks. Input levels are compatible with standard LVTTL and 3.3 V PCI specifications. Each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. The clock input is buffered prior to clocking the R-cells. If not used as a clock it will behave as a regular I/O.
GND Ground
Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 1-5 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state.
TDO, I/O Test Data Output
Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 1-5 on page 1-9). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. When Silicon Explorer II is being used, TDO will act as an output when the "checksum" command is run. It will return to user IO when "checksum" is complete.
TMS Test Mode Select
LOW supply voltage.
HCLK Dedicated (Hardwired) Array Clock
This pin is the clock input for sequential modules. Input levels are compatible with LVTTL or 3.3 V PCI specifications. This input is directly wired to each R-cell and offers clock speeds independent of the number of Rcells being driven. If not used, this pin must be set LOW or HIGH on the board and must not be left floating.
I/O Input/Output
The I/O pin functions as an input, output, tristate or bidirectional buffer. Based on certain configurations, input and output levels are compatible with LVTTL or 3.3 V PCI specifications. Unused I/O pins are automatically tristated by the Designer software.
NC No Connection
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 1-5 on page 1-9). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications.
TRST, I/O Boundary Scan Reset Pin
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
PRA, I/O Probe A/B PRB, I/O
Once it is configured as the JTAG Reset pin, the TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with an internal pull-up resistor. This pin functions as an I/O when the "Reserve JTAG Reset Pin" is not selected in Designer.
VCCI Supply Voltage
The Probe pin is used to output data from any userdefined design node within the device. This independent diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality.
1 -3 8 v2.2
Supply voltage for I/Os. See "Recommended Operating Conditions" on page 1-13. All VCCI power pins in the device should be connected.
VCCA Supply Voltage
Supply voltage for Array. See "Recommended Operating Conditions" on page 1-13. All VCCA power pins in the device should be connected.
Package Pin Assignments
208-Pin PQFP (Top View)
1
208
208-Pin PQFP
Figure 2-1 * 208-Pin PQFP
Note
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v2.2
2-1
208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function GND TDI, I/O I/O NC I/O NC I/O I/O I/O I/O TMS VCCI I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O NC GND VCCA GND I/O TRST, I/O NC I/O I/O I/O NC GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function I/O I/O I/O NC VCCI VCCA I/O I/O I/O I/O I/O I/O NC I/O NC I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
2 -2
v2.2
208-Pin PQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function I/O I/O NC I/O NC PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O QCLKA, I/O I/O PRB,I/O GND VCCA GND NC I/O HCLK VCCI QCLKB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND Pin Number 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function NC I/O NC I/O I/O I/O I/O I/O VCCA VCCI NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O GND VCCA GND NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O
v2.2
2-3
208-Pin PQFP Pin Number 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function NC I/O NC I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O NC NC GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Number 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
208-Pin PQFP A54SX08A A54SX16A A54SX32A A54SX72A Function Function Function Function NC I/O I/O I/O CLKA CLKB NC GND VCCA GND PRA, I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O VCCI NC NC I/O NC I/O I/O TCK, I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O I/O I/O QCLKD, I/O I/O CLKA, I/O CLKB, I/O NC GND VCCA GND PRA, I/O VCCI I/O I/O QCLKC, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O
2 -4
v2.2
100-Pin TQFP (Top View)
100 1
100-Pin TQFP
Figure 2-2 * 100-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v2.2
2-5
100-TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 A54SX08A Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA A54SX16A Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA A54SX32A Function GND TDI, I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA Pin Number 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
100-TQFP A54SX08A Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O A54SX16A Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O A54SX32A Function GND NC I/O HCLK I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O
2 -6
v2.2
100-TQFP Pin Number 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 A54SX08A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O A54SX16A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O CLKA CLKB NC VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O
v2.2
2-7
144-Pin TQFP (Top View)
144 1
144-Pin TQFP
Figure 2-3 * 144-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
2 -8
v2.2
144-Pin TQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A54SX08A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O NC VCCA I/O TRST, I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND A54SX16A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O NC VCCA I/O TRST, I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND A54SX32A Function GND TDI, I/O I/O I/O I/O I/O I/O I/O TMS VCCI GND I/O I/O I/O I/O I/O I/O I/O NC VCCA I/O TRST, I/O I/O I/O I/O I/O I/O GND VCCI VCCA I/O I/O I/O I/O I/O GND Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144-Pin TQFP A54SX08A Function I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O A54SX16A Function I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O A54SX32A Function I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O VCCA GND NC I/O HCLK I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O TDO, I/O I/O
v2.2
2-9
144-Pin TQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A54SX08A Function GND I/O I/O I/O I/O I/O VCCA VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCA NC I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O A54SX16A Function GND I/O I/O I/O I/O I/O VCCA VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCA NC I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O A54SX32A Function GND I/O I/O I/O I/O I/O VCCA VCCI GND I/O I/O I/O I/O I/O I/O I/O VCCA NC I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O GND VCCI I/O I/O I/O I/O I/O I/O Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
144-Pin TQFP A54SX08A Function GND I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O A54SX16A Function GND I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O A54SX32A Function GND I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O TCK, I/O
2 -1 0
v2.2
144-Pin FBGA (Top View)
1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12
Figure 2-4 * 144-Pin FBGA
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v2.2
2-11
144-Pin FGBA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 A54SX08A Function I/O I/O I/O I/O VCCA GND CLKA I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O CLKB I/O I/O I/O GND I/O I/O I/O TCK, I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O A54SX16A Function I/O I/O I/O I/O VCCA GND CLKA I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O CLKB I/O I/O I/O GND I/O I/O I/O TCK, I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O A54SX32A Function I/O I/O I/O I/O VCCA GND CLKA I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O CLKB I/O I/O I/O GND I/O I/O I/O TCK, I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12
144-Pin FGBA A54SX08A Function I/O VCCI TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI VCCI VCCI VCCA I/O GND I/O I/O I/O NC I/O GND GND GND VCCI I/O GND I/O I/O A54SX16A Function I/O VCCI TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI VCCI VCCI VCCA I/O GND I/O I/O I/O NC I/O GND GND GND VCCI I/O GND I/O I/O A54SX32A Function I/O VCCI TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI VCCI VCCI VCCA I/O GND I/O I/O I/O NC I/O GND GND GND VCCI I/O GND I/O I/O
2 -1 2
v2.2
144-Pin FGBA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A54SX08A Function I/O GND I/O I/O GND GND GND VCCI I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCA VCCA VCCI VCCI VCCA I/O I/O NC I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O VCCA A54SX16A Function I/O GND I/O I/O GND GND GND VCCI I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCA VCCA VCCI VCCI VCCA I/O I/O NC I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O VCCA A54SX32A Function I/O GND I/O I/O GND GND GND VCCI I/O I/O I/O I/O TRST, I/O I/O I/O I/O VCCA VCCA VCCI VCCI VCCA I/O I/O NC I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O VCCA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
144-Pin FGBA A54SX08A Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O TDO, I/O I/O A54SX16A Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O TDO, I/O I/O A54SX32A Function I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O TDO, I/O I/O
v2.2
2-13
256-Pin FBGA (Top View)
1 A B C D E F G H J K L M N P R T 2 3 4 56 78 9 10 11 12 13 14 15 16
Figure 2-5 * 256-Pin FBGA
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
2 -1 4
v2.2
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 A54SX16A Function GND TCK, I/O I/O I/O I/O I/O I/O I/O CLKB I/O I/O NC I/O I/O GND GND I/O GND I/O I/O I/O NC I/O VCCA I/O I/O NC I/O I/O I/O GND I/O I/O TDI, I/O GND A54SX32A Function GND TCK, I/O I/O I/O I/O I/O I/O I/O CLKB I/O I/O I/O I/O I/O GND GND I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND I/O I/O TDI, I/O GND A54SX72A Function GND TCK, I/O I/O I/O I/O I/O I/O I/O CLKB, I/O I/O I/O I/O I/O I/O GND GND I/O GND I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND I/O I/O TDI, I/O GND Pin Number C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6
256-Pin FBGA A54SX16A Function I/O NC I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A54SX32A Function I/O I/O I/O I/O I/O CLKA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A54SX72A Function I/O I/O I/O I/O I/O CLKA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRA, I/O QCLKD, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
v2.2
2-15
256-Pin FBGA Pin Number E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5
F6
256-Pin FBGA A54SX72A Function QCLKC, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O VCCI VCCI VCCI VCCI I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND Pin Number G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 A54SX16A Function GND VCCI I/O GND NC VCCA I/O I/O I/O VCCA TRST, I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O NC NC NC NC I/O I/O VCCI GND GND GND GND VCCI I/O A54SX32A Function GND VCCI I/O GND I/O VCCA I/O I/O I/O VCCA TRST, I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND VCCI I/O A54SX72A Function GND VCCI I/O GND I/O VCCA I/O I/O I/O VCCA TRST, I/O I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND GND VCCI I/O
A54SX16A Function I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O TMS I/O I/O VCCI VCCI VCCI VCCI I/O VCCA I/O I/O I/O I/O NC I/O NC I/O I/O VCCI GND GND GND
A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O VCCI VCCI VCCI VCCI I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND GND GND
F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9
2 -1 6
v2.2
256-Pin FBGA Pin Number J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 A54SX16A Function I/O I/O I/O I/O I/O I/O NC VCCA I/O VCCI GND GND GND GND VCCI I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O VCCI VCCI VCCI VCCI I/O I/O I/O I/O I/O A54SX32A Function I/O I/O I/O I/O I/O I/O I/O VCCA I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCI VCCI VCCI I/O I/O I/O I/O I/O A54SX72A Function I/O I/O I/O I/O I/O I/O I/O VCCA I/O VCCI GND GND GND GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCI VCCI VCCI I/O I/O I/O I/O I/O Pin Number L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2
256-Pin FBGA A54SX16A Function NC I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O NC I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND A54SX72A Function I/O I/O I/O I/O I/O I/O I/O QCLKA, I/O PRB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND
v2.2
2-17
256-Pin FBGA Pin Number P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 A54SX16A Function I/O I/O NC I/O I/O I/O I/O NC I/O I/O VCCA I/O I/O I/O I/O GND I/O NC I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O GND GND GND I/O I/O NC I/O A54SX32A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HCLK I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O A54SX72A Function I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O HCLK QCLKB, I/O I/O I/O I/O I/O GND GND GND I/O I/O I/O I/O Pin Number T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
256-Pin FBGA A54SX16A Function I/O I/O I/O VCCA I/O I/O NC I/O I/O TDO, I/O GND A54SX32A Function I/O I/O I/O VCCA I/O I/O I/O I/O I/O TDO, I/O GND A54SX72A Function I/O I/O I/O VCCA I/O I/O I/O I/O I/O TDO, I/O GND
2 -1 8
v2.2
Package Pin Assignments
484-Pin FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Figure 2-6 * 484-Pin FBGA
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v2.2
19
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 A54SX72A Function NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC I/O I/O VCCA I/O I/O I/O I/O I/O I/O
484-Pin FBGA Pin Number AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 A54SX72A Function I/O NC VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O VCCA I/O I/O I/O I/O I/O I/O TDO, I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O VCCI I/O
484-Pin FBGA Pin Number AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 A54SX72A Function I/O I/O I/O QCLKA, I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCI I/O I/O I/O VCCI I/O I/O I/O VCCI
20
v2.2
Package Pin Assignments
484-Pin FBGA Pin Number AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 A54SX72A Function I/O I/O I/O I/O I/O VCCI I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC
484-Pin FBGA Pin Number AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 B9 A54SX72A Function NC NC I/O I/O I/O I/O I/O I/O I/O I/O I/O NC HCLK QCLKB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O I/O I/O
484-Pin FBGA Pin Number B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 A54SX72A Function I/O I/O I/O VCCI CLKA, I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O VCCI I/O I/O VCCI I/O I/O I/O PRA, I/O I/O QCLKD, I/O I/O I/O I/O
v2.2
21
484-Pin FBGA Pin Number C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 A54SX72A Function I/O VCCI I/O I/O I/O I/O I/O I/O I/O TMS I/O VCCI I/O TCK, I/O I/O I/O I/O I/O I/O QCLKC, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND I/O I/O I/O I/O I/O
484-Pin FBGA Pin Number E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 A54SX72A Function I/O I/O I/O GND TDI, IO I/O I/O I/O I/O I/O I/O VCCA CLKB, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O
484-Pin FBGA Pin Number G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 A54SX72A Function I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O VCCI I/O I/O VCCA
22
v2.2
Package Pin Assignments
484-Pin FBGA Pin Number K10 K11 K12 K13 K14 K15 K16 K17 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L10 L11 L12 L13 L14 L15 L16 L17 L22 L23 L24 L25 L26 M1 M2 M3 M4 A54SX72A Function GND GND GND GND GND GND GND GND I/O I/O NC I/O I/O I/O I/O I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O NC I/O I/O I/O
484-Pin FBGA Pin Number M5 M10 M11 M12 M13 M14 M15 M16 M17 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N10 N11 N12 N13 N14 N15 N16 N17 N22 N23 N24 N25 N26 P1 P2 P3 A54SX72A Function I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O GND GND GND GND GND GND GND GND VCCA I/O I/O I/O NC I/O I/O I/O
484-Pin FBGA Pin Number P4 P5 P10 P11 P12 P13 P14 P15 P16 P17 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R10 R11 R12 R13 R14 R15 R16 R17 R22 R23 R24 R25 R26 T1 T2 A54SX72A Function I/O VCCA GND GND GND GND GND GND GND GND I/O I/O VCCI I/O I/O I/O I/O I/O I/O TRST, I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O I/O
v2.2
23
484-Pin FBGA Pin Number T3 T4 T5 T10 T11 T12 T13 T14 T15 T16 T17 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U10 U11 U12 U13 U14 U15 U16 U17 U22 U23 U24 U25 U26 V1 A54SX72A Function I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O GND GND GND GND GND GND GND GND I/O I/O I/O VCCI I/O I/O
484-Pin FBGA Pin Number V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 A54SX72A Function I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O
24
v2.2
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version v2.1 May 2006 Changes in current version (v2.2) RoHS information was added to the "Ordering Information". The Product Plan was removed because all of the devices have been fully characterized. The "Dedicated Mode" section was updated. The "Development Tool Support" section was updated. The "Programming" section was updated. Note 2 was added to Table 1-7 * Absolute Maximum Ratings v2.0 September 2003 A note was added to the "Ordering Information". Note 1 was added to Table 1-8 * Recommended Operating Conditions.
1.
Page ii N/A 1-8 1-11 1-11 1-13 ii 1-13
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
Export Administration Regulations (EAR)
The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
v2.2
1
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